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19-2036; Rev 1; 8/07
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
General Description
The MAX1086-MAX1089 are low-cost, micropower, serial output 10-bit analog-to-digital converters (ADCs) available in a tiny 8-pin SOT23. The MAX1086/MAX1088 operate with a single +5V supply. The MAX1087/MAX1089 operate with a single +3V supply. The devices feature a successive-approximation ADC, automatic shutdown, fast wake-up (1.4s), and a high-speed 3-wire interface. Power consumption is only 0.5mW (VDD = +2.7V) at the maximum sampling rate of 150ksps. AutoShutdownTM (0.1A) between conversions results in reduced power consumption at slower throughput rates. The MAX1086/MAX1087 provide 2-channel, singleended operation and accept input signals from 0 to VREF. The MAX1088/MAX1089 accept true-differential inputs ranging from 0 to VREF. Data is accessed using an external clock through the 3-wire SPITM, QSPITM, and MICROWIRETM-compatible serial interface. Excellent dynamic performance, low-power, ease of use, and small package size, make these converters ideal for portable battery-powered data acquisition applications, and for other applications that demand low power consumption and minimal space.
Features
Single-Supply Operation +3V (MAX1087/MAX1089) +5V (MAX1086/MAX1088) AutoShutdown Between Conversions Low Power 200A at 150ksps 130A at 100ksps 65A at 50ksps 13A at 10ksps 1.5A at 1ksps 0.2A in Shutdown True-Differential Track/Hold, 150kHz Sampling Rate Software-Configurable Unipolar/Bipolar Conversion (MAX1088/MAX1089 only) SPI, QSPI, MICROWIRE-Compatible Interface for DSPs and Processors Internal Conversion Clock 8-Pin SOT23 Package
MAX1086-MAX1089
Ordering Information
PART MAX1086EKA-T MAX1087EKA-T MAX1087ETA+T MAX1088EKA-T TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23 8 SOT23 8 TDFN-EP* 8 SOT23 8 SOT23 TOP MARK AAEZ AAEV AFM AAFB AAEX
Applications
Low Power Data Acquisition Portable Temperature Monitors Flowmeters Touch Screens
MAX1089EKA-T -40C to +85C *EP = Exposed pad. +Denotes a lead-free package. T = Tape and reel.
Pin Configurations
REF
5 4
8 VDD AIN1 (AIN+) AIN2 (AIN-) 1 2 3 8 7 SCLK DOUT CNVST REF
7
GND 4
MAX1086 MAX1087 MAX1088 MAX1089 SOT23-8
6 5
MAX1087 +
1 2 3
AIN1
AIN2
TDFN
AutoShutdown is a trademark of Maxim Integrated Products. SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
GND
VDD
( ) ARE FOR THE MAX1088/MAX1089
CONVST
6
DOUT
TOP VIEW
SCLK
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V CNVST, SCLK, DOUT to GND......................-0.3V to (VDD+0.3V) REF, AIN1(AIN+), AIN2(AIN-) to GND..........-0.3V to (VDD+0.3V) Maximum Current Into Any Pin ...........................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 9.70mW/C above TA = +70C) ......777mW 8-Pin TDFN (derate 18.2mW/C above TA = +70C)...1454.5mW Operating Temperature Ranges.........................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Channel-to-Channel Gain Matching Input Common-Mode Rejection CMR VCM = 0V to VDD; zero scale input INL DNL No missing codes over temperature 0.5 1.0 0.8 0.1 0.1 0.1 10 1.0 1.0 1.0 2.0 Bits LSB LSB LSB LSB ppm/C LSB LSB mV SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS: (fIN (sine-wave) = 10kHz, VIN = 4.096Vp-p for MAX1086/MAX1088 or VIN = 2.5VPP for MAX1087/MAX1089, 150ksps, fSCLK = 8MHz, AIN- = GND for MAX1088/MAX1089) Signal to Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time T/H Acquisition Time Aperture Delay Aperture Jitter Maximum Serial Clock Frequency Duty Cycle fSCLK 8 30 70 tCONV tACQ 30 <50 3.7 1.4 s s ns ps MHz % SINAD THD SFDR -3dB point SINAD > 56dB 61 -70 70 1 100 dB dB dB MHz kHz
2
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.)
PARAMETER ANALOG INPUT Input Voltage Range (Note 4) Input Leakage Current Input Capacitance EXTERNAL REFERENCE INPUT Input Voltage Range VREF VREF = +2.5V at 150ksps Input Current IREF VREF = +4.096V at 150ksps Acquisition/Between conversions DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT) Input Low Voltage Input High Voltage Input Leakage Current Input Capacitance Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage VDD MAX1086/MAX1088 MAX1087/MAX1089 fSAMPLE =150ksps VDD = +3V fSAMPLE =100ksps fSAMPLE =10ksps fSAMPLE =1ksps Positive Supply Current IDD VDD = +5V fSAMPLE =150ksps fSAMPLE =100ksps fSAMPLE =10ksps fSAMPLE =1ksps Shutdown Positive Supply Rejection PSR VDD = 5V 5%; full-scale input VDD = +2.7V to +3.6V; full-scale input 4.75 2.7 5.0 3.0 245 150 15 2 320 215 22 2.5 0.2 0.1 0.1 5 1.0 1.2 mV 400 A 5.25 3.6 350 V COUT VIL VIH IL CIN VOL VOH ISINK = 2mA ISINK = 4mA ISOURCE = 1.5mA CNVST = GND CNVST = GND 15 VDD -0.5 10 15 0.4 0.8 VDD -1 0.1 0.8 V V A pF V V V A pF 1.0 16 26 0.01 VDD +50mV 30 45 1 A V Unipolar Bipolar Channel not selected or conversion stopped 0 -VREF /2 0.01 34 VREF VREF/2 1 V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1086-MAX1089
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3
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
TIMING CHARACTERISTICS (Figures 1 and 2)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088, 0.1F capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C.)
PARAMETERS SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to DOUT Transition SCLK Rise to DOUT Disable CNVST Rise to DOUT Enable CNVST Fall to MSB Valid CNVST Pulse Width SYMBOL tCH tCL tDOT tDOD tDOE tDOV tCSW CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF 30 100 CONDITIONS MIN 38 38 60 500 80 3.7 TYP MAX UNITS ns ns ns ns ns s ns
Note 1: Unipolar input. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 3: Offset nulled. Note 4: The absolute input range for the analog inputs is from GND to VDD.
CNVST
* * *
tCH tCL SCLK * * *
tCSW
tDOE DOUT HIGH-Z * * *
tDOT
tDOD HIGH-Z
Figure 1. Detailed Serial-Interface Timing Sequence
VDD 6k DOUT 6k GND DOUT
CL
CL GND
a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z
a) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z
Figure 2. Load Circuits for Enable/Disable Times 4 _______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
Typical Operating Characteristics
(VDD = +3.0V, VREF = +2.5V for MAX1087/MAX1089 or VDD = +5.0V, VREF = +4.096V for MAX1086/MAX1088, 0.1F capacitor at REF, fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/1089, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX1086-9 toc01
INTEGRAL NONLINEARITY vs. OUTPUT CODE
MAX1086-9 toc02
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
MAX1087/MAX1089 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1086-9 toc03 MAX1086-9 toc06
1.0 0.8 0.6 0.4 INL (LSB)
MAX1087/MAX1089
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1086/MAX1088
1.0
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 400 600 800 1000 1200 OUTPUT CODE
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
OUTPUT CODE
OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
MAX1086-9 toc04
SUPPLY CURRENT vs. SAMPLING RATE
MAX1087/MAX1089
MAX1086-9 toc05
SUPPLY CURRENT vs. SAMPLING RATE
1000 MAX1086/MAX1088
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 200 400 600
MAX1086/MAX1088
1000
SUPPLY CURRENT (A)
10
SUPPLY CURRENT (A)
100
100
10
1
1
800
1000
1200
0.1 0.001
1.0
10
1000
0.1 0.001
1.0
10
1000
OUTPUT CODE
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
380 SUPPLY CURRENT ( A)
MAX1086-9 toc07
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
0.45 SHUTDOWN CURRENT (nA) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05
MAX1086-9 toc08
0.50
330
280
230
180 2.7 3.2 3.7 4.2 4.7 5.2 VDD (V)
0 2.7 3.2 3.7 4.2 4.7 5.2 VDD (V)
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.5V for MAX1087/MAX1089 or VDD = 5.0V, VREF = +4.096V for MAX1086MAX1088, 0.1F capacitor at REF, fSCLK = 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/89, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
380 SUPPLY CURRENT (A)
MAX1086-9 toc09
SHUTDOWN CURRENT vs. TEMPERATURE
MAX1086-9 toc10
OFFSET ERROR vs. TEMPERATURE
0.80 0.60 OFFSET ERROR (LSB) 0.40 0.20 0.00 -0.20 -0.40 0.60 -0.80
MAX1086-9 toc11
300 250 SHUTDOWN CURRENT (nA) 200 150 100 50 0
1.00
330
280
230
180 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-1.00 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1086-9 toc12
GAIN ERROR vs. TEMPERATURE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1086-9 toc13
1.0 0.8 0.6 OFFSET ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2
1.0
-40
-20
0
20
40
60
80
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1086-9 toc14
FFT PLOT (SINAD)
0.00 -20.00 AMPLITUDE (dB) -40.00 -60.00 -80.00
MAX1086-9 toc15
1.0 0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.7 3.2 3.7 4.2 4.7 5.2 VDD (V)
20.00
-100.00 -120.00 -140.00 0 15 30 45 60 FREQUENCY (kHz)
6
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
Pin Description
NAME PIN MAX1086 MAX1087 VDD AIN1 AIN2 GND REF MAX1088 MAX1089 VDD AIN+ AINGND REF FUNCTION
MAX1086-MAX1089
1 2 3 4 5
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V (MAX1086/MAX1088). Bypass with a 0.1F capacitor to GND. Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089) Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089) Ground External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1F capacitor to GND. Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089). Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a conversion and presents the MSB at the completion of a conversion. DOUT goes highimpedance once data has been fully clocked out. Serial Clock Input. Clocks out data at DOUT MSB first. Exposed Pad. Connect the exposed pad to ground or leave unconnected.
6
CNVST
CNVST
7 8 --
DOUT SCLK EP*
DOUT SCLK --
*MAX1087 TDFN package only.
Detailed Description
The MAX1086-MAX1089 analog-to-digital converters (ADCs) use a successive-approximation conversion (SAR) technique and an on-chip track-and-hold (T/H) structure to convert an analog signal into a 10-bit digital result.
The serial interface provides easy interfacing to microprocessors (Ps). Figure 3 shows the simplified internal structure for the MAX1086/MAX1087 (2-channels, single-ended) and the MAX1088/MAX1089 (1-channel, true-differential).
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the MAX1086-MAX1089's input architecture which is composed of a T/H, input multiplexer, comparator, and switched-capacitor DAC. The T/H enters its tracking mode on the rising edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (MAX1086/ MAX1087) or AIN+ (MAX1088/MAX1089). The negative input capacitor is connected to GND (MAX1086/ MAX1087) or AIN- (MAX1088/MAX1089). The T/H enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and CNVST must be held high for a longer period of time. The acquisition time, tACQ, is the maximum time needed for the signal to be acquired, plus the power-up time. It is calculated by the following equation: tACQ = 7 x (RS + RIN) x 24pF + tPWR
7
MAX1086-MAX1089 CNVST SCLK
OSCILLATOR
INPUT SHIFT REGISTER CONTROL
AIN1 (AIN+) AIN2 (AIN-) REF
T/H
10-BIT SAR ADC
DOUT
( ) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
AIN2 AIN1(AIN+) REF GND CIN+ HOLD CINGND(AIN-) HOLD *( ) APPLIES TO MAX1088/1089 VDD/2 TRACK RINRIN+ HOLD DAC
DOUT after 3.7s. Data can then be clocked out using SCLK. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 will be selected for the next conversion.
COMPARATOR +
Selecting Unipolar or Bipolar Conversions (MAX1088/MAX1089)
Initiate true-differential conversions with the MAX1088/MAX1089's unipolar and bipolar modes, using the CNVST pin. AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to V REF . The output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is two's complement. Note: In both modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND by more than 50mV. If unipolar mode is desired (Figure 5a), drive CNVST high to power-up the ADC and place the T/H in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC will then perform a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Be sure to clock out all 12 bits (the 10-bit result plus two sub-bits) of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode will be selected for the next conversion. If bipolar mode is desired (Figure 5b), drive CNVST high for at least 30ns. Next, drive it low for at least 30ns and then high again. This will place the T/H in track mode with AIN+ and AIN- connected to the input capacitors. Now hold CNVST high for t ACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC will then perform a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode will be selected for the next conversion.
Figure 4. Equivalent Input Circuit
where RIN = 1.5k, RS is the source impedance of the input signal, and tPWR = 1s is the power-up time of the device. Note: tACQ is never less than 1.4s and any source impedance below 300 does not significantly affect the ADC`s AC performance. A high impedance source can be accommodated either by lengthening tACQ or by placing a 1F capacitor between the positive and negative analog inputs.
Selecting AIN1 or AIN2 (MAX1086/MAX1087)
Select between the MAX1086/MAX1087's two positive input channels using the CNVST pin. If AIN1 is desired (Figure 5a), drive CNVST high to power-up the ADC and place the T/H in track mode with AIN1 connected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC will then perform a conversion and shutdown automatically. The MSB is available at DOUT after 3.7s. Data can then be clocked out using SCLK. Be sure to clock out all 12 bits of data (the 10-bit result plus two sub-bits) before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 will be selected for the next conversion. If AIN2 is desired (Figure 5b), drive CNVST high for at least 30ns. Next, drive it low for at least 30ns, and then high again. This will power-up the ADC and place the T/H in track mode with AIN2 connected to the positive input capacitor. Now hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the T/H in hold mode. The ADC will then perform a conversion and shutdown automatically. The MSB is available at
Input Bandwidth
The ADCs input tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
8
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
tCONV tACQ CNVST
SCLK
1
4
8
12
DOUT HIGH-Z
B9 MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5a. Single Conversion AIN1 vs. GND (MAX1086/MAX1087), unipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
tCONV tACQ CNVST
SCLK
1
4
8
12
DOUT HIGH-Z
B9 MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5b. Single Conversion AIN2 vs. GND (MAX1086/MAX1087), bipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
Analog Input Protection
Internal protection diodes which clamp the analog input to VDD and GND allow the analog input pins to swing from GND - 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD by more than 50mV or be lower than GND by more than 50mV for accurate conversions. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA.
Internal Clock
The MAX1086-MAX1089 operate from an internal oscillator, which is accurate within 10% of the 4MHz specified clock rate. This results in a worse case conversion time of 3.7s. The internal clock releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to 8MHz.
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
Output Data Format
Figures 5a and 5b illustrate the conversion timing for the MAX1086-MAX1089. The 10-bit conversion result is output in MSB first format, followed by two sub-bits (S1 and S0). Data on DOUT transitions on the falling edge of SCLK. All 12-bits must be clocked out before CNVST transitions again. For the MAX1088/MAX1089, data is straight binary for unipolar mode and two's complement for bipolar mode. For the MAX1086/MAX1087, data is always straight binary.
Transfer Function
Figure 6 shows the unipolar transfer function for the MAX1086-MAX1089. Figure 7 shows the bipolar transfer function for the MAX1088/MAX1089. Code transitions occur halfway between successive-integer LSB values.
Connection to Standard Interfaces
The MAX1086-MAX1089 feature a serial interface that is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the CPU's serial interface as a master, so that the CPU generates the serial clock for the ADCs. Select a clock frequency up to 8MHz.
Applications Information
Automatic Shutdown Mode
With CNVST low, the MAX1086-MAX1089 defaults to an AutoShutdown state (<0.2A) after power-up and between conversions. After detecting a rising edge on CNVST, the part powers up, sets DOUT low and enters track mode. After detecting a falling-edge on CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7s later, the device completes conversion, enters shutdown and MSB is available at DOUT.
How to Perform a Conversion
1) 2) Use a general purpose I/O line on the CPU to hold CNVST low between conversions. Drive CNVST high to acquire AIN1(MAX1086/ MAX1087) or unipolar mode (MAX1088/MAX1089). To acquire AIN2(MAX1086/MAX1087) or bipolar mode (MAX1088/MAX1089), drive CNVST low and high again. Hold CNVST high for 1.4s. Drive CNVST low and wait approximately 3.7s for conversion to complete. After 3.7s, the MSB is available at DOUT. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK's falling edge
OUTPUT CODE
External Reference
An external reference is required for the MAX1086- MAX1089. Use a 0.1F bypass capacitor for best performance. The reference input structure allows a voltage range of +1V to VDD + 50mV.
3) 4)
5)
OUTPUT CODE FULL-SCALE TRANSITION
MAX1088/MAX1089 MAX1086- MAX1089 011 . . . 111 011 . . . 110 FS = VREF 2 ZS = 0 -FS = -VREF 2 V 1LSB = REF 1024
11 . . . 111 11 . . . 110 11 . . . 101
000 . . . 010 000 . . . 001 000 . . . 000 FS = VREF ZS = GND V 1LSB = REF 1024 111 . . . 111 111 . . . 110 111 . . . 101
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSB)
100 . . . 001 100 . . . 000 - FS 0 INPUT VOLTAGE (LSB) *VCOM VREF / 2 *VIN = (AIN+) - (AIN-) +FS - 1LSB
FS FS - 3/2LSB
Figure 6. Unipolar Transfer Function 10
Figure 7. Bipolar Transfer Function
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the P on SCLK's rising-edge. SCLK's rising edge. The first 10 bits are the data and the next two bits are sub-bits (S1, S0). DOUT then goes high impedance (Figure 9b).
MAX1086-MAX1089
SPI and MICROWIRE Interface
When using SPI interface (Figure 8a) or MICROWIRE (Figure 8a and 8b), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on SCLK's rising edge. The first 8-bit data stream contains the first 8-bits of DOUT starting with the MSB. The second 8-bit data stream contains the remaining two result bits (B1, B0) and two trailing sub-bits (S1, S0). DOUT then goes high impedance.
PIC16 and SSP Module and PIC17 Interface
The MAX1086-MAX1089 are compatible with a PIC16/PIC17 microcontroller (C), using the synchronous serial port (SSP) module To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 1 and 2. In SPI mode, the PIC16/PIC17 Cs allow eight bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8-bit data stream contains
QSPI Interface
Using the high-speed QSPI interface (Figure 9a) with CPOL = 0 and CPHA = 0, the MAX1086-MAX1089 support a maximum fSCLK of 8MHz. One 8- to16-bit reading is necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on
I/O SCK MISO VDD
CNVST SCLK DOUT
I/O SK SI
CNVST SCLK DOUT
SPI
MICROWIRE
SS
MAX1086- MAX1089
MAX1086- MAX1089
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
Table 1. Detailed SSPCON Register Content
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX1086-MAX1089 SETTINGS X X 1 0 0 0 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detect Bit Synchronous Serial Port Enable Bit. 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
X = Don't care
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
CNVST 1ST BYTE READ 1 SCLK 4 8 2ND BYTE READ 12 16
DOUT
B9 MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
the first eight data bits starting with the MSB. The second 8-bit data stream contains the remaining bits, D1 through D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one starpoint (Figure 11), connecting the two ground systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) may degrade the performance of the ADC's fast comparator. Bypass VDD to the star ground with a 0.1F capacitor, located as close as possible to the MAX1086-MAX1089s power supply pin. Minimize capacitor lead length for best supply-noise rejection. Add an attenuation resistor (5) if the power supply is extremely noisy.
CS SCK MISO
CNVST SCLK VDD DOUT
QSPI
SS
MAX1086- MAX1089
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
CONTROL BIT SMP CKE D/A P S R/W UA BF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX1086-MAX1089 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care
12 ______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
CNVST
1 SCLK
4
8
12
16
DOUT
B9 MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Definitions
VDD VDD
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1086-MAX1089 are measured using the endpoint method.
SCLK DOUT CNVST
SCK SDI I/O
PIC16/PIC17
MAX1086- MAX1089
GND GND
Differential Nonlinearity
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
Differential nonlinearity (DNL) is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
CNVST 1ST BYTE READ 1 SCLK 4 8 2ND BYTE READ 12 16
DOUT
B9 MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0 LSB
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
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13
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
VLOGIC = +5V/+3V GND
SUPPLIES +3V OR +5V
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
R* = 5 0.1F
VDD
GND
+5V/+3V DGND
Total Harmonic Distortion
MAX1086- MAX1089
*OPTIONAL DIGITAL CIRCUITRY
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 log V22 + V32 + V4 2 + V52 / V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Figure 11. Power-Supply and Grounding Connections
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-todigital noise is caused by quantization error only and results directly from the ADC's resolution (N-bits): SNR = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Chip Information
TRANSISTOR COUNT: 6922 PROCESS: BiCMOS
14
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150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MARKING
MAX1086-MAX1089
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
21-0078
G
1
1
______________________________________________________________________________________
15
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 MAX1086-MAX1089
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
16
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6, 8, &10L, DFN THIN.EPS
150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1086-MAX1089
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
PACKAGE VARIATIONS PKG. CODE T633-2 T833-2 T833-3 T1033-1 T1033-2 T1433-1 T1433-2 N 6 8 8 10 10 14 14 D2 1.500.10 1.500.10 1.500.10 1.500.10 1.500.10 1.700.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.65 BSC 0.50 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEEC MO229 / WEED-3 MO229 / WEED-3 ------b 0.400.05 0.300.05 0.300.05 0.250.05 0.250.05 0.200.05 0.200.05 [(N/2)-1] x e 1.90 REF 1.95 REF 1.95 REF 2.00 REF 2.00 REF 2.40 REF 2.40 REF
0.25 MIN. 0.20 REF.
Revison History
Pages changed at Rev 1: 1, 2, 7, 15, 16, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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